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K9F4008W0A-TCB0, K9F4008W0A-TIB0
Document Title
512K x 8 bit NAND Flash Memory
FLASH MEMORY
Revision History
Revision No. History
0.0 1.0 1.1 Initial issue. 1. Changed Operating Voltage 2.7V ~ 5.5V 3.0V ~ 5.5V Data Sheet 1999 1. Added CE don' care mode during the data-loading and reading t 1. Changed device name - KM29W040AT -> K9F4008W0A-TCB0 - KM29W040AIT -> K9F4008W0A-TIB0 1.Powerup sequence is added : Recovery time of minimum 1s is required before internal circuit gets ready for any command sequences
~ 2.5V
Draft Date
April 10th 1998 July 14th 1998 April 10th 1999
Remark
Preliminary
1.2
Sep. 15th 1999
1.3
Jul. 23th 2001
~ 2.5V
VCC High
WP
WE
2. AC parameter tCLR(CLE to RE Delay, min 50ns) is added. 3. AC parameter tAR is devided into tAR1, tAR2 ALE to RE Delay tAR 250 (before revision) ns
1
(after revision) ALE to RE Delay(ID Delay) ALE to RE Delay(Read Cycle) tAR1 tAR2 20 250 ns ns
Note : For more detailed features and specifications including FAQ, please refer to Samsung' Flash web site. s http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you.
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K9F4008W0A-TCB0, K9F4008W0A-TIB0
512K x 8 Bit NAND Flash Memory
FEATURES
* Voltage Supply: 3.0V~5.5V * Organization - Memory Cell Array : 512K x 8 bit - Data Register : 32 x 8 bit * Automatic Program and Erase (Typical) - Frame Program : 32 Byte in 500s - Block Erase : 4K Byte in 6ms * 32-Byte Frame Read Operation - Random Access : 15s(Max.) - Serial Frame Access : 120ns(Min.) * Command/Address/Data Multiplexed I/O port * Low Operation Current (Typical) - 10A Standby Current - 10mA Read/ Program/Erase Current * Reliable CMOS Floating-Gate Technology - Endurance : 100K Program/Erase Cycles * Package - 44(40) - Lead TSOP Type II (400mil / 0.8 mm pitch)
FLASH MEMORY
GENERAL DESCRIPTION
The K9F4008W0A is a 512Kx8bit NAND Flash Memory. Its NAND cell structure provides the most cost-effective solution for Digital Audio Recording. A Program operation programs a 32-byte frame in typical 500s and an Erase operation erase a 4K-byte block in typical 6ms. Data in a frame can be read out at a burst cycle rate of 120ns/byte. The I/O pins serve as the ports for address and data input/output as well as for command inputs. The on-chip write controller automates the program and erase operations, including program or erase pulse repetition where required, and performs internal verification of cell data. The K9F4008W0A is an optimum solution for flash memory application that do not require the high performance levels or capacity of larger density flash memories. These application include data storage in digital Telephone Answering Devices(TAD) and other consumer applications that require voice data storage.
PIN CONFIGURATION
PIN DESCRIPTION
Pin Name I/O0 ~ I/O7 CLE Pin Function Data Inputs/Outputs Command Latch Enable Address Latch Enable Chip Enable Read Enable Write Enable Write Protect Ground Input Ready/Busy output Power Ground No Connection
VSS CLE ALE WE WP N.C N.C N.C N.C N.C
N.C N.C N.C N.C N.C I/O0 I/O1 I/O2 I/O3 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
VCC CE RE R/B GND N.C N.C N.C N.C N.C
ALE CE RE WE WP GND
N.C N.C N.C N.C N.C I/O7 I/O6 I/O5 I/O4 VCC
R/B VCC VSS N.C
44(40) TSOP (II)
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC, VSS or GND inputs disconnected.
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K9F4008W0A-TCB0, K9F4008W0A-TIB0
Figure 1. FUNCTIONAL BLOCK DIAGRAM
A7 - A18 X-Buffers Latches & Decoders Y-Buffers Latches & Decoders
FLASH MEMORY
4M Bit NAND Flash ARRAY 32Byte x 4Frames x 4096Rows
A0 - A6
Page Register & S/A Command Command Register Y-Gating I/O Buffers & Latches
CE RE WE
Control Logic & High Voltage Generator
I/O0 Global Buffers I/O7
CLE ALE WP
Figure 2. ARRAY ORGANIZATION
Good Block
1Block = 32 Rows = 4K Bytes The 1st Block (4KB) 4K Rows (=128 Blocks) 1 Frame = 32 Bytes 1 Row = 4 Frames = 128 Bytes 1 Block = 32 Rows = 4K Bytes 1 Device = 32Bytes x 4Frames x 32Rows x 128Blocks = 4Mbits 8 bit 128Bytes
1
2
3
4
Frame Register 32 Bytes
I/O0 ~ I/O7
I/O0 1st Cycle 2nd Cycle 3rd Cycle A0 A8 A16
I/O1 A1 A9 A17
I/O2 A2 A10 A18
I/O3 A3 A11 X*
(1)
I/O4 A4 A12 X*
I/O5 A5 A13 X*
I/O6 A6 A14 *X
I/O7 A7 A15 *X
Column Address (A0-A4) Frame Address (A5-A6) Row Address (A7-A11) Block Address (A12-A18)
NOTE : *(1) : X can be VIL or VIH * The device ignores any additional input of address cycles than reguired.
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K9F4008W0A-TCB0, K9F4008W0A-TIB0
PRODUCT INTRODUCTION
FLASH MEMORY
The K9F4008W0A is a 4M bit memory organized as 4096 rows by 1024 columns. A 256-bit data register is connected to memory cell arrays accommodating data transfer between the registers and the cell array during frame read and frame program operations. The memory array is composed of unit NAND structures in which 8 cells are connected serially. Each of the 8 cells reside in a different row. A block consists of the 32 rows, totaling 4096 unit NAND structures of 8bits each. The array organization is shown in Figure 2. The program and read operations are executed on a frame basis, while the erase operation is executed on a block basis. The memory array consists of 128 separately erasable 4K-byte blocks. The K9F4008W0A has addresses multiplexed into 8 I/O pins. This scheme not only reduces pin count but allows systems upgrades to higher density flash memories by maintaining consistency in system board design. Command, address and data are all written through I/Os by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle except for Block Erase command which requires two cycles. For byte-level addressing, the 512K byte physical space requires a 19-bit address, low row address and high row address. Frame Read and frame Program require the same three address cycles following by a command input. In the Block Erase operation, however, only the two row address cycles are required. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9F4008W0A.
Table 1. COMMAND SETS
Function Read Reset Frame Program Block Erase Status read Read ID 1st. Cycle 00h FFh 80h 60h 70h 90h 2nd. Cycle 10h D0h O O Acceptable Command during Busy
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
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K9F4008W0A-TCB0, K9F4008W0A-TIB0
PIN DESCRIPTION
Command Latch Enable(CLE)
FLASH MEMORY
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high.
Chip Enable(CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode. However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to standby mode.
Write Enable(WE)
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one.
I/O Port : I/O0 ~ I/O7
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z when the chip is deselected or when the outputs are disabled.
Write Protect(WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low.
Ready/Busy(R/B)
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled.
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K9F4008W0A-TCB0, K9F4008W0A-TIB0
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Temperature Under Bias Storage Temperature K9F4008W0A-TCB0 K9F4008W0A-TIB0 TSTG Symbol VIN TBIAS
FLASH MEMORY
Rating -0.6 to +7.0 -10 to +125 -40 to +125 -65 to +150 Unit V C C
NOTE : 1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. 2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, K9F4008W0A-TCB0:TA=0 to 70C, K9F4008W0A-TIB0:TA=-40 to 85C)
Parameter Supply Voltage Supply Voltage Symbol VCC VSS Min 3.0 0 Typ. 0 Max 5.5 0 Unit V V
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
Parameter Burst Read Cycle Operating Current Program Erase Symbol ICC1 ICC2 ICC3 ISB1 ISB2 ILI ILO VIH VIL VOH VOL IOL(R/B) IOH=-400A IOL=2.1mA VOL=0.4V Test Conditions tRC=120ns,CE=VIL, IOUT=0mA CE=VIH, WP=0V/VCC CE=VCC-0.2, WP=0V/VCC VIN=0 to 5.5V VOUT=0 to 5.5V Vcc = 3.0V ~ 3.6V Min 2.4 -0.3 2.4 8 Typ 5 5 5 10 10 Max 10 10 10 1 50 10 10 VCC+ 0.3 0.6 0.4 Vcc = 3.6V ~ 5.5V Min 2.4 -0.3 2.4 8 Typ 10 10 10 10 10 Max 20 20 20 1 50 10 10 VCC+ 0.5 0.8 0.4 mA V A mA Unit
Stand-by Current(TTL) Stand-by Current(CMOS) Input Leakage Current Output Leakage Current Input High Voltage, All inputs Input Low Voltage, All inputs Output High Voltage Level Output Low Voltage Level Output Low Current(R/B)
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K9F4008W0A-TCB0, K9F4008W0A-TIB0
VALID BLOCK
Parameter Valid Block Number Symbol NVB Min 125 Typ. -
FLASH MEMORY
Max 128 Unit Block
NOTE : 1. The K9F4008W0A may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks. 2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction.
AC TEST CONDITION
(K9F4008W0A-TCB0:TA=0 to 70C, K9F4008W0A-TIB0:TA=-40 to 85C, VCC=3.0V ~ 5.5V unless otherwise noted) Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load Value Vcc=3.0V ~ 3.6V 0.4V to 2.6V 5ns 0.8V and 2.0V 1 TTL GATE and CL = 100pF Vcc=3.6V ~ 5.5V 0.4V to 2.6V
CAPACITANCE(TA=25C, Vcc=5.0V, f=1.0MHz)
Item Input / Output Capacitance Input Capacitance Symbol CI/O CIN Test Condition VIL=0V VIN=0V Min Max 10 10 Unit pF pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE H L H L L L L X X X X ALE L H L H L L L X X X(1) X CE L L L L L L L X X X H H H X X X X H X X X X WE RE H H H H H WP X X H H H X X H H L 0V/VCC(2) Read Mode Mode Command Input Address Input(3clock) Command Input Address Input(3clock)
Write Mode Data Input
Sequential Read & Data Output During Read(Busy) During Program(Busy) During Erase(Busy) Write Protect Stand-by
NOTE : 1. X can be VIL or VIH 2. WP should be biased to CMOS high or CMOS low for standby.
Program/Erase Characteristics
Parameter Program Time Number of Partial Program Cycles in the Same Frame Block Erase Time Symbol tPROG Nop tBERS Min Typ 0.5 6 Max 1 10 10 Unit ms cycles ms
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K9F4008W0A-TCB0, K9F4008W0A-TIB0
AC Timing Characteristics for Command / Address / Data Input
Parameter CLE Set-up Time CLE Hold Time CE Setup Time CE Hold Time WE Pulse Width ALE Setup Time ALE Hold Time Data Set-up Time Data Hold Time Write Cycle Time WE High Hold Time Symbol tCLS tCLH tCS tCH tWP tALS tALH tDS tDH tWC tWH Min 50 50 50 50 60 50 50 40 20 120 40
FLASH MEMORY
Max Unit ns ns ns ns ns ns ns ns ns ns ns
AC Characteristics for Operation
Parameter Data Transfer from Cell to Register ALE to RE Delay(ID Delay) ALE to RE Delay(Read Cycle) CE low to RE low (ID read) CLE to RE Delay Ready to RE Low RE Pulse Width WE High to Busy Read Cycle Time RE Access Time RE High to Output Hi-Z CE High to Output Hi-Z RE High Hold Time Output Hi-Z to RE Low CE High to Ready(in case of interception by CE at read) RE Low to Status Output CE Low to Status Output WE High to RE Low RE access time(Read ID) Device Resetting Time(Read/Program/Erase) Symbol tR tAR1 tAR2 tCR tCLR tRR tRP tWB tRC tREA tRHZ tCHZ tREH tIR tCRY tRSTO tCSTO tWHR tWHRID tRST Min 20 250 250 50 100 60 120 0 40 0 50 100 Max 15 200 50 30 50 100+tr(R/B) 60 70 5/10/500
(1)
Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s
NOTE : 1. The time to Ready depends on the value of the pull-up resistor tied R/B pin.
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K9F4008W0A-TCB0, K9F4008W0A-TIB0
NAND Flash Technical Notes
Invalid Block(s)
FLASH MEMORY
Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The information regarding the invalid block(s) is called as the invalid block information. The invalid block information is written to the 1st or the 2nd page of the invalid block(s) with 00h data. Devices with invalid block(s) have the same quality level or as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction.
Identifying Invalid Block(s)
All device locations are erased(FFh) except locations where the invalid block information is written prior to shipping. Since the invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based on the original invalid block information and create the invalid block table via the following suggested flow chart(Figure 1). Any intentional erasure of the original invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
Create (or update) Invalid Block(s) Table
No
Check "FFh" ?
*
Check "FFh" on the 1st and 2nd page
Yes No
Last Block ?
Yes
End
Figure 1. Flow chart to create invalid block table.
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K9F4008W0A-TCB0, K9F4008W0A-TIB0
K9F4008W0A Technical Notes(Continued)
Error in program or erase operation
FLASH MEMORY
Over its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks.
Failure Mode Block Frame Single Bit Erase Failure Program Failure Program Failure ("1" --> "0")
Detection and Countermeasure sequence Read after Erase --> Block Replacement Status Read after Program --> Block Replacement Block Verify after Program --> Block Replacement
Block Replacement
1st (n-1)th nth (page)
{ {
Block A 2 an error occurs. Buffer memory of the controller. Block B 1
1st (n-1)th nth (page)
* Step1 When an error happens in the nth page of the Block ' during erase or program operation. A' * Step2 Copy the nth page data of the Block ' in the buffer memory to the nth page of another free block. (Block ' ) A' B' * Step3 Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ' . B' * Step4 Do not erase or program to Block ' by creating an ' A' invalid Block'table or other appropriate scheme.
During Erase operation ;
When the error occurs after an erase operation, prevent future accesses to this bad block (again by creating a table within the system or other appropriate scheme.)

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K9F4008W0A-TCB0, K9F4008W0A-TIB0
System Interface Using CE don' t-care.
FLASH MEMORY
For a easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 32byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and reading would provide significant savings in power consumption.
Figure 3. Program Operation with CE don' t-care. CLE
CE don' t-care
CE
WE ALE
I/O0~7
80h
Start Add.(3Cycle)
Data Input
Data Input
10h
tCS CE
(Max. 60ns)
tCH CE
tCEA
tREA tWP WE I/O0~7 out RE
Timing requirements : If CE is is exerted high during sequential data-reading, the falling edge of CE to valid data(tCEA) must be kept greater than 60ns.
Figure 4. Read Operation with CE don' t-care.
CLE
t-care CE don'
CE
Must be held low during tR.
RE ALE R/B tR
WE
I/O0~7
00h
Start Add.(3Cycle)
Data Output(sequential)
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K9F4008W0A-TCB0, K9F4008W0A-TIB0
* Command Latch Cycle
FLASH MEMORY
CLE tCLS tCS CE tCLH tCH
tWP WE
tALS ALE tDS I/O0~7
tALH
tDH
Command
* Address Latch Cycle
tCLS CLE
tCS CE
tWC
tWC
tWP WE tWH tALS ALE tDS I/O0~7 tDH
tWP tWH
tWP
tALH
tDS
tDH
tDS
tDH
A0~A7
A8~A15
A16~A18
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K9F4008W0A-TCB0, K9F4008W0A-TIB0
* Input Data Latch Cycle
FLASH MEMORY
tCLH CLE
tCH CE
tALS ALE
tWC
tWP WE tDS I/O0~7 tWH tDH
tWP
tDH
tWP tDH
tDS
tDS
DIN 0
DIN 1
DIN 31
* Burst Read Cycle After Frame Access(CLE=L, WE=H, ALE=L)
CE
tRC tRP tREA tREH tRHZ*
RE tRHZ tRHZ*
I/O0~7 tRR R/B
Dout
tREA
tREA
Dout
Dout
NOTES : Transition is measured200mV from steady state voltage with load. This parameter is sampled and not 100% tested.
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K9F4008W0A-TCB0, K9F4008W0A-TIB0
* Status Read Cycle
tCLR CLE tCLH tREA CE tCH tWP WE tWHR RE tDS I/O0~7 70h tDH tIR tRSTO tCSTO
FLASH MEMORY
tCHZ
tRHZ
Status Output
READ OPERATION(READ ONE FRAME)
CLE
CE
WE tWB tAR2 ALE tR RE tRR I/O0~7
00h
tCHZ
tRC
tRHZ
A0 ~ A7
A8 ~ A15
A16 ~ A18
Dout N
Dout N+1 Dout N+2 Dout N+3 Dout 32
Column Address
Row Address Busy
R/B
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K9F4008W0A-TCB0, K9F4008W0A-TIB0
READ OPERATION(INTERCEPTED BY CE)
FLASH MEMORY
CLE
CE
WE tWB tAR2 ALE tR RE tRR I/O0~7
00h
tCHZ
A0~A7
A8~A15
A16~A18
Dout N
Dout N+1
Dout N+2
Dout N+3
Column Address
Row Address Busy
R/B
PROGRAM OPERATION
CLE
CE tWC WE tWB ALE tPROG tWC tWC
RE
Din Din N N+1 1 up to 32 Byte Data Serial Input Din 31
I/O0~7
80h
A0 ~ A7 A8 ~ A15 A16 ~ A18 Row Address
10h Program Command
70h Read Status Command
I/O0
Sequential Data Column Input Command Address
15
R/B
I/O0=0 Successful Program I/O0=1 Error in Program
K9F4008W0A-TCB0, K9F4008W0A-TIB0
BLOCK ERASE OPERATION
FLASH MEMORY
CLE
CE
WE tWB ALE tBERS
RE
I/O0~7
60h
A8~A15
A16~A18
DOh
Block Address
Auto Block Erase Setup Command
Erase Command
16
R/B
Busy
K9F4008W0A-TCB0, K9F4008W0A-TIB0
DEVICE OPERATION
FRAME READ
FLASH MEMORY
Upon initial device power up or after excution of Reset(FFh) command, the device defaults to Read mode. This operation is also initiated by writing 00h to the command register along with three address cycles. The three cycle address input must be given for access to each new frame. The read mode is enabled when the frame address is changed. 32 bytes of data within the selected frame are transferred to the data registers in less than 15s(tR). The CPU can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a frame is loaded into the registers, they may be read out in 120ns cycle time by sequentially pulsing RE with CE staying low. High to low transitions of the RE clock output the data starting from the selected column address up to the last column address within the frame(column 32).
Figure 3. Read Operation
CLE CE WE ALE RE R/B I/O0~7
00h Start Add.(3Cycle) A0~A7 & A8~A18
Busy(Seek Time)
Data Output(Sequential)
Seek Time
0
31
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K9F4008W0A-TCB0, K9F4008W0A-TIB0
FRAME PROGRAM
FLASH MEMORY
The device is programmed on a frame basis. The addressing may be done in random order in a block. A frame program cycle consist of a serial data loading period in which up to 32 bytes of data must be loaded into the device, and a nonvolatile programming period in which the loaded data is programmed into the appropriate cells. The sequential data loading period begins by inputting the frame program setup command(80h), followed by the three cycle address input and then sequential data loading. The bytes other than those to be programmed do not need to be loaded. The frame Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write controller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the CPU for other tasks. The CPU can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the frame Program is complete, the Write Status Bit(I/O0) may be checked. The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register.
Figure 4. Frame Program Operation tPROG R/B I/O0~7
80h
Address & Data Input A0~A7 & A8~A18 32 Byte Data
10h
FRAME PROGRAM
While the frame size of the device is 32 Bytes, not all the bytes in a frame have to be programmed at once. The device supports partial frame programming in which a frame may be partially programmed up to 10 separate program operations. The program size in each of the 10 partial program operations is freely determined by the user and do not have to be equal to each other or to any preset size. However, the user should ensure that the partial program units within a frame do not overlap as "0" data cannot be changed to "1" data without an erase operation. To perform a partial frame program operation, the user only writes the partial frame data that is to programmed. Just as in the standard frame program operation, an 80h command is followed by start address data. However, only the partial program data need be divided when programming a frame in 10 partial program operations.
Figure 5. Example of Dividing a Frame into 10 Partial Program Units
1st partial program start address (00h) 2nd partial program start address (04h) 3rd partial program start address (06h) : : : : : : 9th partial program start address (18h) 10th partial program start address (1Fh) FA A2 43 CB 81 28 E0 2A D5 - - - - - - 32 B5 7D 6F AA E1 D7 C0 Single Frame
10th partial frame program data 9th partial frame program data : : : : : : 3rd partial frame program data 2nd partial frame program data 1st partial frame program data
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K9F4008W0A-TCB0, K9F4008W0A-TIB0
BLOCK ERASE
FLASH MEMORY
The Erase operation is done 4K Bytes(1 block) at a time. Block address loading is accomplished in two cycles initiated by an Erase Setup command(60h). Only address A12 to A18 are valid while A8 to A11 is ignored. The Erase Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles erase, erase-verify and pulse repetition where required.
Figure 6. Block Erase Operation tBERS R/B I/O0~7
60h
Address Input(2Cycle) Block Add. : A8~A18
D0h
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is complete, and whether the program or erase operation completed successfully. After writing 70h command to the command register, a read cycle outputs the contents of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, the required read command(00h) should be input before serial page read cycle.
Table2. Read Status Register Definition
I/O # I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Device Operation Write Protect Reserved for Future Use Status Program Definition "0" : Successful Program "1" : Error in Program "0" "0" "0" "0" "0" "0" "0" : Busy "0" : Protected "1" : Ready "1" : Not Protected
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K9F4008W0A-TCB0, K9F4008W0A-TIB0
RESET
FLASH MEMORY
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during the read, program or erase mode, the reset operation will abort these operation. In the case of Reset during Program or Erase operations, the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The device enters the Read mode after completion of Reset operation as shown Table 3. If the device is already in reset state a new reset command will not be accepted to by the command register. The R/B pin transitions to low for tRST after the Reset command is written. Reset command is not necessarily for normal device operation. Refer to Figure 7 below.
Figure 7. RESET Operation tRST
R/B I/O0~7
FFh
Table3. Device Status
After Power-up Operation Mode Read After Reset Read
20
K9F4008W0A-TCB0, K9F4008W0A-TIB0
Figure 9. Read ID Operation
FLASH MEMORY
CLE CE
tCLR tCEA tWHR
WE ALE RE I/O0~7
tAR1
tREA
90h Add. Input(1Cycle) A0~A7:"0" Dout(ECh) Maker code Dout(A4H) Device code
21
Package Dimensions
READY/BUSY
FLASH MEMORY
The device has a R/B output that provides a hardware method of indicating the completion of a frame program, erase or read seek completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or a random read is begin after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 10). Its value can be determined by the following guidance.
Rp VCC
ibusy
Ready Vcc R/B open drain output 0.8V Busy 2.0V
tf GND Device
tr
Fig 10 Rp vs tr ,tf & Rp vs ibusy
@ Vcc = 3.3V, Ta = 25C , CL = 100pF
3.3 381
tr,tf [s]
1.65
200n tr 100n
96 4.2
189
1.1 0.825
2m 1m
tf
4.2
4.2
4.2
1K
2K
3K Rp(ohm)
4K
Rp value guidance
Rp(min) = VCC(Max.) - VOL(Max.) IOL + IL = 3.2V 8mA + IL
where IL is the sum of the input currents of all devices tied to the R/B pin. Rp(max) is determined by maximum permissible limit of tr
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Ibusy [A]
300n
Ibusy
290
3m
Package Dimensions
DATA PROTECTTION
FLASH MEMORY
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down and recovery time of minimum 1s is required before internal circuit gets ready for any command sequences as shown in Figure 11. The two step command sequence for program/erase provides additional software protection.
Figure 11. AC Waveforms for Power Transition
~ 2.5V VCC High
~ 2.5V
WP
WE
23
10s
Package Dimensions
PACKAGE DIMENSIONS
44(40) LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(II) 44(40) - TSOP2 - 400F
FLASH MEMORY
Unit :mm/Inch
0~8 0.25 TYP 0.010 #44(40) #23(21) 0.45~0.75 0.018~0.030 11.760.20 0.4630.008 10.16 0.400 0.50 0.020 #1 #22(20)
+0.10
0.15 -0.05
+0.004 0.006 -0.002
18.410.10 0.7250.004
1.000.10 0.0390.004
1.20 Max. 0.047
18.81 Max. 0.741
0.10 MAX 0.004 0.05 Min. 0.002
(
0.805 ) 0.032
0.350.10 0.0140.004
0.80 0.0315
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